The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device having a wafer burn-in test mode.
In general, semiconductor memory devices such as DDR SDRAM (Double Data Rate Synchronous DRAM) have a variety of test modes for screening unstable circuit in the devices. Among the above modes, a burn-in test mode is used to screen unstable circuits in a semiconductor memory device by applying a stress such that the semiconductor memory device operates with a high driving voltage at a high temperature.
Examples of the burn-in test mode are a wafer burn-in test mode for performing a burn-in test in a wafer level, and a packet burn-in test mode for performing a burn-in test in a packet level after completion of a wafer test.
In general, because a small number of pads are used, a wafer burn-in test mode is used to screen defects only in a core region of the device where a band including a plurality of cell arrays is disposed. Thereafter, a package burn-in test mode is used to screen defects not only in the core region but also in a peripheral region where reading/writing/precharging circuits are disposed.
FIG. 1 is a partial block diagram of a conventional semiconductor memory device having a wafer burn-in test mode. For reference, a pad to which an external power voltage is applied, a pad to which a ground voltage is applied, a pad to which an internal power voltage is applied, a pad to which a wafer burn-in mode signal WBI_ENT is applied, and ‘A<8>, A<9>, A<11>, A<12>’ address pads are used in a wafer burn-in test mode.
Referring to FIG. 1, the conventional semiconductor memory device includes a path selector 110, an enable signal generator 120, a decoding unit 130, a latch unit 140, and a core region controller 150.
In response to a wafer burn-in mode signal WBI_ENT, the path selector 110 outputs signals, that are received through an ‘A<8>’ address pad, an ‘A<9>’ address pad, an ‘A<11>’ address pad, and an ‘A<12>’ address pad, to normal transmission paths NOR_A<8>, NOR_A<9>, NOR_A<11> and NOR_A<12> or test transmission paths WBI_A<8>, WBI_A<9>, WBI_A<11> and WBI_A<12>.
The enable signal generator 120 receives a signal through the ‘WBI_A<8>’ test transmission path corresponding to the ‘A<8> address pad, and generates an enable signal EN_PUL that is activated for a predetermined period. The enable signal EN_PUL is used to control a signal input operation of the latch unit 140. When the enable signal EN_PUL is activated, several wafer burn-in test mode signals are input into the latch unit 140.
FIG. 2 is a diagram illustrating the enable signal generator 120 of FIG. 1.
Referring to FIG. 2, the enable signal generator 120 includes a first delay unit 122, an inverting delay unit 124, and an output unit 126. The first delay unit 122 delays the signal received through the ‘WBI_A<8> test transmission path by a predetermined time. The inverting delay unit 124 inverts the output signal of the first delay unit 122 and delays the resulting signal by a predetermined period. The output unit 126 receives the output signal of the first delay unit 122 and the output signal of the inverting delay unit 124 to output the enable signal EN_PUL. The output enable signal EN_PUL is a pulse signal that has a pulse width reflected in the inverting delay unit 124.
Referring again to FIG. 1, the decoding unit 130 decodes signals received through the test transmission paths WBI_A<9>, WBI_A<11> and WBI_A<12> to generate a plurality of decoding signals DCD_TM<1:7> and a reset signal RST. Thus, the decoding unit 130 is a 3×8 decoder that receives signals through the test transmission paths WBI_A<9>, WBI_A<11> and WBI_A<12> to output seven decoding signals DCD_TM<1:7> and a reset signal RST.
In response to the enable signal EN_PUL output from the enable signal generator 120, the latch unit 140 latches the seven decoding signals DCD_TM<1:7> output form the decoding unit 130 and outputs seven test mode signals WBI_TM<1:7>. The latch unit 140 is initialized in response to the reset signal RST output from the decoding unit 130.
The core region controller 150 controls a plurality of cell arrays disposed in a core region according to seven test mode signals WBI_TM<1:7>, so that stresses can be applied to the cell arrays in seven wafer burn-in test modes. For example, under the control of the core region controller 150, all word lines connected to all the cell arrays, odd-numbered word lines, even-numbered word lines, or a given word line may be driven to apply a stress to the corresponding cell array.
The simple operation of FIG. 1 will be described below.
In the wafer burn-in test mode, the signals received through the ‘A<8>’ address pad, the ‘A<9>’ address pad, the ‘A<11>’ address pad, and the ‘A<12>’ address pad are transmitted to the test transmission paths WBI_A<8>, WBI_A<9>, WBI_A<11> and WBI_A<12> according to the wafer burn-in mode signal WBI_ENT. The signals transmitted through the test transmission paths WBI_A<9>, WBI_A<11> and WBI_A<12> are decoded to generate seven decoding signals DCM_TM<1:7> and a reset signal RST. The decoding signals DCM_TM<1:7> are latched in response to the enable signal EN_PUL, outputted as seven test mode signals WBI_TM<1:7>, and input into the core region controller 150. The core region controller 150 applies a stress to the cell array in up to seven wafer burn-in test modes.
As described above, the wafer burn-in test mode uses a small number of pads and thus is sufficient for screening only the defects in the core region. Therefore, a new test mode cannot be added.
Also, because too many word lines are driven in the wafer burn-in test mode, the stress conditions for a sense amplifier cannot be created easily. Therefore, it is difficult to screen a sense amplifier.